As DRAM devices are designed with greater densities, the photo process used to make them becomes increasingly difficult, since the design rule must be continually reduced. For example, in a 256 Mbit DRAM, the design rule has been reduced to less than 0.2 micrometers. In order to solve this problem, a photoresist (PR) flow process has been adopted. In the PR flow process, however, the PR flow amounts vary depending upon the design sizes. As a result, there are difficulties in applying this process.
FIGS. 1A to 1D illustrate the conventional method for forming contacts in a semiconductor device.
Referring to FIG. 1A, a device isolating region 12 is initially formed to define an active region in a semiconductor substrate 10. A cell transistor is then formed over the semiconductor substrate 10. As is generally well known, in forming the cell transistor, a gate electrode is formed by sequentially stacking a gate oxide layer (not shown), a polysilicon layer 14a, and a silicide layer 14b. Furthermore, a source/drain region (not shown) is formed in the semiconductor substrate 10 along both sides of the gate electrode layers 14a and 14b. Then, in order to insulate the gate electrode layers 14a and 14b, a gate mask 14c is formed over the silicide layer 14b to complete the gate electrode stack 14, and a nitride spacer 15 is formed on side walls of the polysilicon layer 14a and the silicide layer 14b.
A first inter-layer insulating layer 16 is then formed over the semiconductor substrate 10, covering the gate electrode stack 14. The first inter-layer insulating layer 16 may be, for example, a BPSG layer. Then, the first inter-layer insulating layer 16 is flattened using a BPSG flow process and a chemical mechanical polishing (CMP) process. The first inter-layer insulating layer 16 is then etched using a contact hole forming mask 18 until the semiconductor substrate 10 of the cell region is exposed, thereby forming a self-aligned contact pad forming contact holes 20.
Referring to FIG. 1B, a polysilicon layer (not shown) is formed over the first inter-layer insulating layer 16, filling the contact holes 20. Then the polysilicon layer is etched using an etch-back process or a CMP process, and thus self-aligned contact pads 22a and 22b, i.e., a DC pad 22a and a BC pad 22b, are formed. The DC pad 22a and the BC pad 22b are each electrically connected to the semiconductor substrate 10.
Then, a second inter-layer insulating layer 24 is formed over the first inter-layer insulating layer 16, covering the self-aligned pads 22a and 22b. The second inter-layer insulating layer may be, for example, a PE-TEOS layer. The second inter-layer insulating layer 24 is then etched, using a first contact hole forming mask 26, until the surfaces of the cell region and the DC pad 22a are exposed. In this manner, a bit line DC contact hole 27 is formed.
As shown in FIG. 1C, the first contact hole forming mask 26 is then removed. After that, the second and first inter-layer insulating layers 24 and 16 are sequentially etched by using a second contact hole forming mask 28, until the surface of the semiconductor substrate 10 in the core region is exposed, thereby forming a core DC contact hole 29.
As described above, as DRAM devices achieve higher densities, it becomes very difficult to simultaneously form DCs both at the cell array region and in the core/peripheral region since two different fine patterns are required for the cell array region and core/peripheral region. Therefore, the photo process for DC formation cannot be applied simultaneously to both the cell array region and the core/peripheral region.
Referring to FIG. 1D, the second contact hole forming mask 28 is removed. Then, a polysilicon layer 30 is formed over the second inter-layer insulating layer 24, filling both the bit line DC contact hole 27 and the core DC contact hole 29. The polysilicon layer 30 is then flattened in such a manner that some thickness of the second inter-layer insulating layer 24 remains. Then, a bit line forming tungsten silicide layer 32 is formed over the polysilicon layer 30.
Finally, the silicide layer 32 and the polysilicon layer 30 are sequentially etched using a bit line forming mask (not shown). As a result, bit lines are formed that are electrically connected through the direct contacts of the cell region and the core region to the DC pad 22a and to the semiconductor substrate 10.
The above-mentioned method uses two photolithography processes for the formation of DCs both at the cell array region and in the core/peripheral region, resulting in process complexity and high manufacturing cost. Accordingly, there is a need of a method that can form a direct contact at the cell array region and at the peripheral region using a simple process having a low cost.